Researchers on the
IEEE Digital Elements and Know-how Convention (ECTC) final week pushed the cutting-edge in a expertise that’s turning into important to cutting-edge processors and reminiscence. Known as hybrid bonding, the expertise stacks two or extra chips atop one another in the identical bundle, permitting chipmakers to extend the variety of transistors of their processors and reminiscences regardless of a basic slowdown within the tempo of the standard transistor shrinking that when outlined Moore’s Legislation. Analysis teams from main chipmakers and universities demonstrated a wide range of hard-fought enhancements, with a couple of—together with from Utilized Supplies, Imec, Intel, and Sony—exhibiting outcomes that would result in a file density of connections between 3D stacked chips of round 7 million hyperlinks in a sq. millimeter of silicon.
All these connections are wanted due to the brand new nature of progress in semiconductors, Intel’s
Yi Shi informed engineers at ECTC. As Intel basic supervisor of expertise improvement Ann Kelleher defined to IEEE Spectrum in 2022, Moore’s Legislation is now ruled by an idea referred to as system expertise co-optimization, or STCO. In STCO, a chip’s features, similar to cache reminiscence, enter/output, and logic are separated out and made utilizing the perfect manufacturing expertise for every. Hybrid bonding and different superior packaging tech can then reassemble them in order that they work like a single piece of silicon. However that may solely occur with a excessive density of connections that may shuttle bits between items of silicon with little delay or power consumption.
Hybrid bonding isn’t the one superior packaging expertise in use, but it surely offers the very best density of vertical connections. And it dominated ECTC, making up about one-fifth of the analysis offered, in accordance with
Chris Scanlan, senior vice chairman of expertise at Besi, whose instruments had been behind a number of of the breakthroughs.
“It’s troublesome to say what would be the restrict. Issues are shifting very quick.”
—Jean-Charles Souriau, CEA Leti
In hybrid bonding, copper pads are constructed on the high face of every chip. The copper is surrounded by insulation, normally silicon oxide, and the pads themselves are barely recessed from the floor of the insulation. After the oxide is chemically modified, the 2 chips are then pressed collectively face-to-face, so the recessed pads align with every. This sandwich is then slowly heated, inflicting the copper to broaden throughout the hole, connecting the 2 chips.
Hybrid bonding can both connect particular person chips of 1 measurement to a wafer filled with chips of a bigger measurement or used to bond two full wafers of chips of the identical measurement collectively. Thanks partially to its use in digicam chips, the latter is a extra mature course of than the previous. Imec, for instance, reported a number of the
most dense wafer-on-wafer (WoW) bonds ever with a bond-to-bond distance (or pitch) of simply 400 nanometers. The identical analysis middle managed a 2-micrometer pitch for the chip-on-wafer (CoW) state of affairs. (Business chips at present have connections about 9 μm aside.)
Hybrid bonding begins by forming recessed copper pads on the high of the chip [top]. The encircling oxide dielectric bonds when the 2 chips are pressed collectively [middle]. Annealing expands the copper to type a conductive connection [bottom].
“With the gear obtainable, it’s simpler to align wafer to wafer than chip to wafer. Most processes for microelectronics are made for [full] wafers,” says
Jean-Charles Souriau, scientific chief in integration and packaging on the French analysis group, CEA Leti. Nonetheless, it’s chip-on-wafer (or die-to-wafer) that’s making a splash in high-end processors similar to AMD’s Epyc line, the place the approach is used to assemble compute cores and cache reminiscence in its superior CPUs and AI accelerators.
In pushing for tighter and tighter pitches for each situations, researchers targeted on making surfaces fractionally flatter, getting certain wafers to stay collectively higher, and slicing the time and complexity of the entire course of. Getting it proper might finally imply enabling a revolution in how chips are designed.
WoW, these are some tight pitches
The wafer-on-wafer (WoW) analysis that reported the tightest pitches—500 nm to 360 nm—all spent a variety of effort on one factor: flatness. To bind two wafers along with 100-nm-level accuracy, the entire wafer must be almost completely flat. If it’s bowed or warped, complete sections of the supplies gained’t join.
Flattening wafers is the job of a course of referred to as chemical mechanical planarization, or CMP. It’s key to chipmaking usually, particularly for the components of the method that produce the layers of interconnects above the transistors.
“CMP is a key parameter we’ve got to regulate for hybrid bonding,” says Souriau. Outcomes offered this week at ECTC took CMP to a different stage, not simply flattening throughout the wafer however decreasing mere nanometers of roundness on the insulation between the copper pads to make sure higher connections.
Different analysis targeted on making certain these flattened components caught collectively strongly sufficient by experimenting with completely different floor supplies similar to silicon carbonitride as an alternative of silicon oxide or by utilizing completely different schemes to chemically activate the floor. Initially, when wafers or dies are pressed collectively, they’re held in place with comparatively weak hydrogen bonds, and the priority is making certain that every part stays in place between the bonding and additional steps. Sure wafers and chips are then heated slowly (a course of referred to as annealing) to type stronger chemical bonds. Simply how sturdy these bonds are—and tips on how to even determine that out—was the topic of a variety of analysis at ECTC.
A part of that ultimate bond energy would come from the copper connections as effectively. The annealing step expands the copper throughout the hole to type a conductive bridge. Controlling the scale of that hole is vital, defined Samsung’s
Seung Ho Hahn. An excessive amount of of a spot and the copper gained’t join. Too little and it’ll push the wafers aside. It’s a matter of nanometers, and Hahn reported analysis on a brand new chemical course of that hopes to get it excellent by etching away the copper a single atomic layer at a time.
The standard of the connection counts, too. Even after the copper expands, most schemes confirmed that the metallic’s grain boundaries don’t cross from one facet to a different. Such a crossing reduces a connection’s electrical resistance and will enhance its reliability. Researchers at Tohoku College in Japan reported a brand new metallurgical scheme that would lastly generate giant, single grains of copper that cross the boundary. “This can be a drastic change,” mentioned
Takafumi Fukushima, an affiliate professor at Tohoku College. “We at the moment are analyzing what underlies it.”
“I feel it’s doable to make greater than 20-layer stack utilizing this expertise.”
—Hyeonmin Lee, Samsung
Different experiments targeted on streamlining the hybrid bonding course of. A number of sought to scale back the annealing temperature wanted to type bonds—sometimes round 300 °C—motivated by the potential to scale back any threat of harm to the chips from the extended heating. And researchers from
Utilized Supplies offered progress on a way to radically scale back the time wanted for annealing—from hours to only 5 minutes.
CoWs which might be excellent within the subject
Chip-on-wafer (CoW) hybrid bonding is extra helpful to trade in the meanwhile: It permits chipmakers to stack chiplets of various sizes collectively, and to check every chip earlier than it’s certain to a different, making certain that they aren’t fatally dooming an costly CPU with a single flawed half.
However CoW comes with all the difficulties of WoW and fewer of the choices to alleviate them. For instance, CMP is designed to flatten wafers, not particular person dies. As soon as dies have been minimize from their supply wafer and examined, there’s much less that may be executed to enhance their readiness for bonding.
Nonetheless, Intel reported CoW hybrid bonds with a 3-μm pitch, and Imec managed 2 μm, largely by making the transferred dies very flat whereas they had been nonetheless connected to the wafer and holding them additional clear going ahead. Efforts by each teams used plasma etching to cube up the dies as an alternative of the standard methodology, which makes use of a specialised blade. Plasma gained’t result in chipping on the edges, which creates particles that interferes with connections. It additionally allowed the Imec group to form the die, making
chamfered corners that relieved mechanical stress that would break connections.
CoW hybrid bonding goes to be important to the way forward for high-bandwidth reminiscence (HBM), a number of researchers informed
IEEE Spectrum. HBM is a stack of DRAM dies atop a management logic chip—presently 8 to 12 dies excessive. Typically positioned inside the identical bundle as high-end GPUs, HBM is essential to offering the tsunami of information wanted to run giant language fashions like ChatGPT. As we speak, HBM dies are stacked utilizing so-called microbump expertise, wherein tiny balls of solder between every layer are surrounded by an natural filler.
However with AI pushing reminiscence demand even increased, DRAM makers wish to do 20 layers or extra in HBM chips. Nonetheless, the amount microbumps take up imply that these stacks will quickly be too tall to slot in the bundle with GPUs. Hybrid bonding wouldn’t simply shrink the peak of HBMs, it also needs to make it simpler to take away extra warmth from the bundle, as a result of there’s much less thermal resistance between its layers.
A 200-nanometer WoW pitch isn’t just doable, however fascinating.
At ECTC, Samsung engineers confirmed {that a} hybrid bonding scheme might make a 16-layer HBM stack. “I feel it’s doable to make greater than 20-layer stack utilizing this expertise,” mentioned
Hyeonmin Lee, a senior engineer at Samsung.
Different new CoW expertise might assist deliver hybrid bonding to high-bandwidth reminiscence. Although they didn’t current analysis on this at ECTC, researchers at
CEA Leti are engaged on so-called self-alignment expertise, says Souriau. That will assist guarantee CoW connections utilizing chemical processes. Some components of every floor could be made hydrophobic and a few hydrophilic, leading to surfaces that will slide into place mechanically.
At ECTC, researchers at Tohoku College and Yamaha Robotics reported work on an identical scheme, utilizing the floor rigidity of water to align 5-μm pads on experimental DRAM chips with higher than 50-nm accuracy.
How far can hybrid bonding go?
Researchers will virtually definitely maintain pushing the pitch of hybrid bonding connections. A 200-nm WoW pitch isn’t just doable however fascinating,
Han-Jong Chia, a program supervisor pathfinding methods at Taiwan Semiconductor Manufacturing Co., informed engineers at ECTC. Inside two years, TSMC plans to introduce a expertise referred to as bottom energy supply. (Intel plans it for the top of this yr.) That’s a expertise that places the chip’s chunky power-delivery interconnects beneath the silicon as an alternative of above it. With these out of the way in which, the uppermost interconnect ranges can join higher to smaller hybrid bonding bond pads, TSMC researchers calculate. Again facet energy supply with 200-nm bond pads would minimize down the capacitance of 3D connections a lot that the product of power effectivity and sign delay could be as a lot as 9 instances as excessive as what may be achieved with 400-nm bond pads.
In some unspecified time in the future sooner or later, if bond pitches are narrowed even additional, Chia instructed, it’d develop into sensible to “fold” blocks of circuitry so they’re constructed throughout two wafers. That method a number of the longer connections inside the block is likely to be made shorter by the vertical pathway, doubtlessly dashing computations and decreasing energy consumption.
And hybrid bonding is probably not restricted to silicon. “As we speak there’s a variety of improvement in silicon-to-silicon wafers, however we’re additionally trying to do hybrid bonding between gallium nitride and silicon wafers and glass wafers…every part on every part,” says CEA Leti’s Souriau. His group even offered analysis on hybrid bonding for quantum-computing chips, which entails aligning and binding superconducting niobium as an alternative of copper.
“It’s troublesome to say what would be the restrict,” Souriau says. “Issues are shifting very quick.”
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